1. ______ is used in logic design of VLSI.
a) LIFO
b) FIFO
c) FILO
d) LILO
Explanation: First in first out (FIFO) technique and finite state machine technique is used in the logic design of the VLSI circuits
2. Which provides higher integration density?
a) switch transistor logic
b) transistor buffer logic
c) transistor transistor logic
d) circuit level logic
Explanation:Transistor-transistor logic offers higher integration density and it became the first integrated circuit revolution.
3.Physical and electrical specification is given in ____________
a) architectural design
b) logic design
c) system design
d) functional design
Explanation: Functional design defines the major functional units of the system, interconnections, physical and electrical specifications.
4. Which is the high level representation of VLSI design?
a) problem statement
b) logic design
c) HDL program
d) functional design
Explanation: Problem statement is a high level representation of the system. Performance, functionality and physical dimensions are considered here
5. Gate minimization technique is used to simplify the logic.
a) true
b) false
Explanation: Gate minimization technique is used to find the simplest, smallest and effective implementation of the logic
6. nMOS fabrication process is carried out in ____________
a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals
Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with high purity
7. ______________ impurities are added to the wafer of the crystal.
a) n impurities
b) p impurities
c) siicon
d) crystal
Explanation: p impurities are introduced as the crystal is grown. This increases the hole concentration in the device
8. What kind of substrate is provided above the barrier to dopants?
a) insulating
b) conducting
c) silicon
d) semiconducting
Explanation: Above a layer of silicon dioxide which acts as a barrier, an insulating layer is provided upon which other layers may be deposited and patterned.
9. The photoresist layer is exposed to ____________
a) Visible light
b) Ultraviolet light
c) Infra red light
d) LED
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.
10. In nMOS device, gate material could be ____________
a) silicon
b) polysilicon
c) boron
d) phosphorus
Explanation: In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.