1.In saturation mode operation, gate to drain capacitance is zero due to ___________
a) Gate and drain are interconnected
b) Channel length is reduced
c) Inversion layer doesn’t exist
d) Drain is connected to ground
Explanation: Due to the pinched off channel, the capacitance between source to drain is reduced to zero.
2. When MOSFET is operating in saturation region, the gate to source capacitance is?
a) 1/2*Cox*W*L
b) 2/3*Cox*W*L
c) Cox*W*L
d) 1/3*Cox*W*L
Explanation: Due to the reduction in channel length, gate to drain and gate to substrate capacitance are zero, the gate to channel capacitance as seen between the gate and the source is approximately defined as 2/3*Cox*W*L.
3. The load capacitance is measured between ___________
a) Output node and input node
b) Output node and Vcc
c) Output node and ground
d) Input node and ground
Explanation: The load capacitance is measured at output node and ground.
4. The load capacitance is equivalent to ___________
a) Sum of all lumped linear capacitances between input and output node
b) Sum of all junction capacitance between Vcc and ground
c) Sum of all junction capacitance between input and output
d) Sum of all lumped linear capacitances between output node and ground
Explanation: The load capacitance is measured by sum of all lumped linear capacitances between input and output node.
5. Interconnect capacitance contributes to the load capacitance when the CMOS inverters are connected in cascade configuration.
a) True
b) False
Explanation: In cascade configuration the load capacitance is measured by sum of all the lumped capacitances and interconnect capacitance.
6. Interconnect capacitance is formed due to ___________
a) Junction capacitance between gate and substrate
b) Wire connecting the gates of 2 different inverters
c) Parasitic capacitance existing between metal and polysilicon connection between 2 inverters
d) All of the mentioned
Explanation: Parasitic capacitance existing between metal and polysilicon connection between 2 inverters causes the interconnect capacitance.
7. Which of the following parameters are found using load capacitance?
a) Delay time
b) Power consumption
c) Speed of the CMOS logic
d) All of the mentioned
Explanation: Using load capacitance, delay time, power consumption, speed of the CMOS logic can be measured.
8.The difference output of the basic differential amplifier is taken at ___________
a) At X and ground
b) At Y and ground
c) Difference of the voltages at the gates of M1 and M2
d) Difference of the voltages between X and Y
Explanation: Difference of the voltages between X and Y
9. The Differential output of the difference amplifier is the amplification of __________
a) Difference between the voltages of input signals
b) Difference between the output of the each transistor
c) Difference between the supply and the output of the each transistor
d) All of the mentioned
Explanation: Difference between the voltages of input signals
10. The inputs to the differential amplifier are applied at __________
a) At X and Y
b) At the gates of M1 and M2
c) All of the mentioned
d) None of the mentioned
Explanation: The inputs to the differential amplifier are applied at the gates of M1 and M2