1. pMOS is ____________
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
Explanation: nMOS is acceptor doped and pMOS is donor doped devices. Acceptor doped forms p-type region and donor doped forms n-type region
2. Inversion layer in enhancement mode consists of excess of ____________
a) positive carriers
b) negative carriers
c) both in equal quantity
d) neutral carriers
Explanation: Inversion layer in enhancement mode consists of excess of negative carriers that is electron.
3. What is the condition for linear region?
a) Vgs lesser than Vt
b) Vgs greater than Vt
c) Vds lesser than Vgs
d) Vds greater than Vgs
Explanation: The condition for linear region is Vgs > Vt. The power of MOS in the linear region is less. It is a power dissipating region.
4. As source drain voltage increases, channel depth ____________
a) increases
b) decreases
c) logarithmically increases
d) exponentially increases
Explanation: As source drain voltage Vds increases, the channel depth at the drain end decreases
5. VLSI technology uses ________ to form integrated circuit.
a) transistors
b) switches
c) diodes
d) buffers
Explanation: Very large scale integration is the process of creating an integrated circuit with thousands of transistors into one single chip
6. Medium scale integration has ____________
a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates
Explanation: Small scale integration has one or more logic gate. Further improved technology is medium scale integration which consists of hundred logic gates. Large scale integration has thousand logic gates
7. The difficulty in achieving high doping concentration leads to ____________
a) error in concentration
b) error in variation
c) error in doping
d) distribution error
Explanation: As photolithography comes closer to the fundamental law of optics, achieving high accuracy in doping concentration becomes difficult, which leads to error due to variation.
8. _________ is used to deal with effect of variation.
a) chip level technique
b) logic level technique
c) switch level technique
d) system level technique
Explanation: Designers must simulate multiple fabrication process or use system level technique for dealing with effects of variation.
9. As die size shrinks, the complexity of making the photomasks ____________
a) increases
b) decreases
c) remains the same
d) cannot be determined
Explanation: As the die size shrinks due to scaling, the number of die per wafer increases and the complexity of making the photomasks increases rapidly.
10. ______ architecture is used to design VLSI.
a) system on a device
b) single open circuit
c) system on a chip
d) system on a circuit
Explanation: SoC that is system on a chip architecture is used to design the very high level integrated circuit.