1. BiCMOS has _______ standby leakage current.
a) higher
b) lower
c) very low
d) none of the mentioned
Explanation: BiCMOS has higher standby leakage current and thus has high power consumption.
2. For improved base current discharge ________ enhancement type nMOS devices have to be added.
a) two
b) three
c) one
d) four
Explanation: For improved base current discharge, two enhancement type nMOS transistors have to be added
3. The BJTs in the BICMOS circuit is in _____________ configuration.
a) Push-pull
b) Totem pole
c) Active high
d) Active low
Explanation: In BiCMOS circuit, the BJT transistors are in Totem pole configuration.
4. The MOSFETS are arranged in this configuration to provide __________
a) Zero static power dissipation
b) High Input impedance
c) Both zero static power dissipation and high input impedance
d) None of the mentioned
Explanation: MOSFETs provide zero static power dissipation and high input impedance
5. In latch-up condition, parasitic component gives rise to __________ conducting path.
a) low resistance
b) high resistance
c) low capacitance
d) high capacitance
Explanation: In latch-up condition, the parasitic component gives rise to low resistance conducting path between Vdd and Vss with disastrous results. Careful control during fabrication is necessary to avoid this problem.
6. Latch-up can be induced by __________
a) incident radiation
b) reflected radiation
c) etching
d) diffracted radiation
Explanation: Latch-up can be induced by glitches on the supply rail or by incident radiation
7. How many transistors might bring up latch up effect in p-well structure?
a) two
b) three
c) one
d) four
Explanation: Two transistors and two resistances might bring up the latch-up effect in p-well structure. These are associated with p-well and with regions of the substrate.
8. Substrate doping level should be decreased to avoid the latch-up effect.
a) true
b) false
Explanation: An increase in substrate doping level with a consequent drop in the value of Rs can be used as a remedy for latch-up problem.
9. What can be introduced to reduce the latch-up effect?
a) latch-up rings
b) guard rings
c) latch guard rings
d) substrate rings
Explanation:The introduction of guard rings can reduce the effect of latch-up problem. Guard rings are diffusions which decouple the parasitic bipolar transistors
10. Which process produces a circuit which is less prone to latch-up effect?
a) CMOS
b) nMOS
c) pMOS
d) BiCMOS
Explanation: BiCMOS process produces circuits that are less likely to suffer from latch-up problems where as CMOS circuits are very highly prone to latch-up problems.