VLSI Design Questions and Answers - Latch-up in CMOS Part-2

1. Which one of the following is the main factor for reducing the latch-up effect?
a) reduced p-well resistance
b) reduced n-well resistance
c) increased n-well resistance
d) increased p-well resistance

Answer: b
Explanation: One of the main factors in reducing the latch-up effect is reduced n-well resistance Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and higher value of holding current is also required.

2. The parasitic PNP transistor has the effect of _______ carrier lifetime.
a) increasing
b) decreasing
c) exponentially decreasing
d) exponentially increasing

Answer: b
Explanation: The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region.

3. The reduction in carrier lifetime brings about __________
a) reduction in alpha
b) reduction in beta
c) reduction in current
d) reduction in voltage

Answer: b
Explanation: The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region which results in radiation in beta.

4. To reduce latch-up effect substrate resistance should be high.
a) true
b) false

Answer: b
Explanation: To reduce the latch-up effect, substrate resistance Rs should be low. Reduction of Rs and Rw means that larger lateral current is necessary to invite latch-up

5.. Latch-up is the generation of __________
a) low impedance path
b) high impedance path
c) low resistance path
d) high resistance path

Answer: a
Explanation: Latch-up is the generation of low-impedance path in CMOS chips between the power supply and ground rails.

6. Latch-up is brought about by BJTs __________
a) with positive feedback
b) with negative feedback
c) with no feedback
d) without BJT

Answer: a
Explanation: Latch-up occurs due to BJTs for silicon-controlled rectifiers with positive feedback and virtually short circuit the power and ground rail.

7. Sudden transient in power can cause latch-up.
a) true
b) false

Answer: a
Explanation: Sudden transient in power and ground buses are also among the reason which causes latch-up effect

8. BJT gain should be ______ to avoid latch-up effect.
a) increased
b) decreased
c) should be maintained constant
d) changed randomly

Answer: b
Explanation: BJT gain should be reduced by lowering the minority carrier lifetime through doping of the substrate to lower the latch-up effect.

9. Stick diagrams are those which convey layer information through?
a) thickness
b) color
c) shapes
d) layers

Answer: b
Explanation: Stick diagrams are those which convey layer information through color codes. Thickness is not considered in this stick diagram representation

10. Which color is used for n-diffusion?
a) red
b) blue
c) green
d) yellow

Answer: c
Explanation: Green color is used to show the presence of n-diffusion layer. The n-type diffusion will dope the source or drain region in the p-well region.