1. Small disturbances of noise ___________
a) decreases the inverter voltage
b) increases the output voltage
c) switches the inverter stage between 0 to 1
d) does not switch the stage and keeps it stable
Explanation: Small disturbances of noise switches the inverter stage between 0 and 1 or vice versa. It disturbs the normal operation or behaviour.
2. The buffer speeds up the ___________
a) rise time
b) fall time
c) all of the mentioned
d) none of the mentioned
Explanation: The buffer speeds up the rise time of propogated signal edge. A buffer is the combination of two inverters in which one output is fed to the other as the input.
3. Overall delay increases as n ___________
a) increases
b) decreases
c) exponentially decreases
d) logarithmically decreases
Explanation: Overall delay increases as n increases where n is the number of pass transistors connected in series.
4. Which contributes to the wiring capacitance?
a) fringing fields
b) interlayer capacitance
c) peripheral capacitance
d) all of the mentioned
Explanation: The sources of capacitances that contribute to the total wiring capacitance are fringing field capacitance, interlayer capacitance and peripheral capacitance.
5. What does the value d in fringing field capacitance measures?
a) thickness of wire
b) length of the wire
c) wire to substrate separation
d) wire to wire separation
Explanation: The quantity d in fringing field capacitance measures the wire to substrate separation. It is the distance between the wire and the substrate used in the device.
6. Total wire capacitance is equal to ___________
a) area capacitance
b) fringing field capacitance
c) area capacitance + fringing field capacitance
d) peripheral capacitance
Explanation: Total wire capacitance can be given as the sum of area capacitance and fringing field capacitance.
7. Interlayer capacitance occurs due to ___________
a) separation between plates
b) electric field between plates
c) charges between plates
d) parallel plate effect
Explanation: Interlayer capacitance occurs due to a parallel plate effect between one layer and another. When one capacitance value comes closer to another they create some combined effects.
8. Which capacitance must be higher?
a) metal to polysilicon capacitance
b) metal to substrate capacitance
c) metal to metal capacitance
d) diffusion capacitance
Explanation: Metal to polysilicon capacitance should be higher than metal to substrate capacitance. This is due to that when one layer underlies the other and in consequence interlayer capacitance is highly dependent on layout.
9. Peripheral capacitance is given in _________ eper unit length.
a) nano farad
b) pico farad
c) micro farad
d) farad
Explanation: Peripheral capacitance is given in picofarads per unit length. This is the sidewall capacitance. Each diode has this side wall capacitance.
10. For greater relative value of peripheral capacitance ___________ should be small.
a) source area
b) drain area
c) source & drain area
d) none of the mentioned
Explanation: The smaller the source or drain area, the greater the relative value of peripheral capacitance as they are both inversely related.