1. What will be the values of the following variables after MOD operations?
x = 5 MOD 3;
y = -5 MOD 3;
z = 5 MOD -3;
a) x = 2, y = -2 and z = -2
b) x = 2, y = 1 and z = -2
c) x= 2, y = -2 and z = 2
d) x = 2, y = -2 and z = 1
Explanation: MOD takes the sign of divisor which is the second operand, but not of first operand. In the first operand, it will simply give the remainder which is 2. In the second statement, the modulo will not contain negative, it will simply divide and the result will be 1. This is done by adding 3*2 in -5, in that case 1 is left, therefore modulo is 1. But, in third statement, divisor is negative so it will be taken as -(5 MOD 3).
2. What will be the values of following variables after REM operations?
x = 5 REM 3;
y = -5 REM 3;
z = 5 REM -3;
a) x= 2, y = 1 and z = -2
b) x = 2, y = -2 and z = 1
c) x = 2, y = -2 and z = 2
d) x = 2, y = 1 and z = 1
Explanation: Here, REM operator is used, which takes the sign of dividend instead of divisor unlike MOD operator. In case of negative divisor, the sign is ignored. Therefore, in first statement, the remainder is calculated normally, which is 2. In second statement, it will be considered as -(5 REM 3). In third statement, it is simply solved like first statement, ignoring the negative sign
3. XNOR is a logical operator in VHDL.
a) True
b) False
Explanation: XNOR is a logical operator representing Ex-NOR operation and was introduced in VHDL 93. In the previous versions, there was no XNOR operator and to perform Ex-NOR, we needed to implement it by using XOR itself
4. The most basic form of behavioral modeling in VHDL is _______
a) IF statements
b) Assignment statements
c) Loop statements
d) WAIT statements
Explanation: Assignment statements are used basically in the behavioral modeling. In behavioral modeling, one needs to describe the value of outputs for various combinations of inputs, so we need to assign different values to output variables. Therefore, the assignment is the most used statement in behavioral modeling
5. For any concurrent assignment statement, which of the following is true?
a) The statement is executed once
b) The statement is executed twice
c) The value of left operand is assigned to right operand
d) The statement is executed as many times as the value changes
Explanation: A concurrent assignment statement assigns the value of right operand to left operand and this statement is executed many times. Whenever the value of right operand is changed, the assignment statement is executed.
6. a < = b after 10ns; In this statement the keyword ‘after’ is used for introducing delay.
a) True
b) False
Explanation: The keyword ‘after’ is used for introducing delay in the assignment statement. Whenever the value of b is changed, the value of a is changed after 10ns. This 10ns is helpful while creating square waveform.
7. Which of the circuit is described by following VHDL code?.
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_func IS
PORT(x, a, b : IN std_logic;
q : OUT std_logic);
END my_func;
ARCHITECTURE behavior OF my_func IS
SIGNAL s : INTEGER;
BEGIN
WITH s SELECT
q <= a AFTER 10 ns WHEN 0;
b AFTER 10 ns WHEN 1;
s <= 0 WHEN x = ‘0’ ELSE
1 WHEN x = ‘1’;
END behavior;
a) AND gate
b) OR gate
c) MUX 2:1
d) DEMUX 1:2
Explanation: In this code, the behavior of 2:1 MUX is explained. By using WITH statement, the output is selected by the use of select line. Here, s is used as select line and x is considered as the value of select line. Also, a and b are taken as two inputs and q as output.
8.The main problem with behavioral modeling is ________
a) Asynchronous delays
b) Simulation
c) No delay
d) Supports single driver only
Explanation: In behavioral modeling, there are different types of delays and this can create problem in functioning of system. Sometimes zero delay events are used to produce consistent results. If these are not properly ordered, results can be disparate between different simulations.
9. What is the use of simulation deltas in VHDL code?
a) To create delays in simulation
b) To assign values to signals
c) To order some events
d) Evaluate assignment statements
Explanation: Simulation deltas are used to order some specific events to avoid complications in simulations. Especially, in zero delay events, they are properly ordered so as to produce consistent results. It is actually a complex delay model used for zero delay events
10. VHDL can’t handle multiply driven signals.
a) True
b) False
Explanation: A multiply driven signal is the one which has more than one driver. VHDL can handle these signals easily and in a unique way. These multiply driven signals are useful for modeling various data bus and bidirectional bus etc.