1. What is the basic unit of structural modeling?
a) Process
b) Component declaration
c) Component instantiation
d) Block
Explanation: Structural modeling describes the design at the component level. Like behavioral modeling is described by using processes, similarly, structural modeling is described by using component instantiation. Both processes and component instantiation are described in the architecture body
2. Which of the following is similar to the entity declaration in structural modeling?
a) Component instantiation
b) Component declaration
c) Port map
d) Generic map
Explanation: Component declaration in structural modeling is similar to the entity declaration. It describes the external interface of the component or subcomponent. All the input and output ports are declared in the component declaration part.
3. What do you mean by component instantiation?
a) To use the component
b) To describe external interface of the component
c) To declare the gate level components
d) To remove any component from the design
Explanation: Component instantiation means to use the component in the circuit. Declaration of component just declares the input and outputs of the component but its instantiation describes its interconnection with other components and to port it in the circuit.
4. The structural model is similar to___________
a) Boolean relations of the circuit
b) Schematic block diagram of the circuit
c) Timing relations of the circuit
d) Components of the circuit
Explanation:The structural modeling in VHDL is similar to the schematic block diagram of the circuit. Just like block diagram defines the components and interconnection between them, same is the case with structural modeling.
5. Which of the following is the correct syntax for component instantiation?
a) instantiate : component_name PORT MAP (port_list);
b) label : instantiate COMPONENT PORT MAP (port_list);
c) label : component_name PORT MAP (port_list);
d) label : instantiate component_name PORT MAP (port_list)
Explanation: Component instantiation is done in the architecture part by using some label and the function called PORT MAP(). The name of the component is followed by the function PORT MAP (). The arguments list of the function contains the name of ports in the same order as they were declared. By using this we can define the interconnection between ports.
6. It is possible to use a component twice which was declared only once.
a) True
b) False
Explanation: There is no restriction on the number of times a component can be used whose declaration is done. It is needed to be declared only once. Just using two or more different labels, we can use the same component again and again.
7. Which of the following must be known to describe a structural model in VHDL?
a) Number of inputs and outputs
b) Components and their connections
c) Relation between inputs and outputs
d) Value of output for different input combinations
Explanation: It is necessary to know the whole circuit at the component level and how these components are interconnected with each other. Since structural model describes the input and output ports of a design, so we need the components and their connections.
8. Which of the following is the correct order for a structural model in VHDL?
a) Libraries, Entity declaration, Component declaration, Component instantiation
b) Libraries, Component declaration, Entity declaration, Component instantiation
c) Libraries, Entity declaration, Component instantiation, Component declaration
d) Component declaration, Libraries, Entity declaration, Component instantiation
Explanation: In a VHDL code, first of all, the packages and libraries are declared which are then followed by entity declaration. After the entity is declared, to model a circuit on the structural level, first all the components are declared after which they can be instantiated.
9. There is a special function called interconnect () to define interconnections between pins.
a) True
b) False
Explanation: There is no special function for defining interconnection between two or more inputs or outputs. These interconnections are defined by using port map only. When we use same port for two or more components then they are interconnected.
10. Refer to the architecture given below, there are two outputs called x and y. The structure defined is a full adder circuit. Which of the outputs corresponds to sum output of the adder?
ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, y);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, x);
END arch1;
a) y
b) x
c) s5
d) c
Explanation: Since there are three components which are two inputs EXOR gate, AND gate and OR gate. The signal s1 is the output of EXOR of a and b inputs. This signal is further used to EXOR with c and the output is y. So, y = a EXOR b EXOR c, which corresponds to the sum output of the full adder.