1.A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the transport delay model is used?
a) 20 ns
b) 30 ns
c) 40 ns
d) Output will remain zero
Explanation: In case of transport delay model, all the spikes and pulses, no matter how small, are taken into consideration i.e. not swallowed down. Transport delay order the events rather than just scheduling the last event. Therefore, when the buffer is executed at 10 ns, it will schedule a 1 at B at 30 ns. After which, it is again executed at 20 ns and hence the output will be zero again at 40 ns.
2. For zero delay events, which of the following mechanism is used?
a) Transport delay mechanism
b) Inertial delay mechanism
c) Delta delay mechanism
d) Preemption delay mechanism
Explanation: For zero delay events, The output can disparate between two different simulation runs. For example, in a complex circuit, if we are using a NAND gate then the output can be affected by the order of the events, like AND operation first and after that NOT operation can produce some different result whereas it opposite order can produce some different result. Therefore, to avoid this at the time of simulation, we use the simulation delta delay model
3. Which of the following delay model follows the principle of preemption?
a) Inertial delay
b) Transport delay
c) Delta delay
d) Wire delay
Explanation: Preemption technique means that only last event is taken into consideration whereas preceding events can be ignored. Same is the case with inertial delay model in which only last value of output is considered ignoring all the previous events or pulses or spikes etc.
4. Which of the following is not the application of inertial delay?
a) Buffer delay
b) PC wire line delay
c) Simple delay in OR gate
d) Inverter delay
Explanation: The inertial delay can be used for any of the logic circuit may it be a logic gate or any combinational circuit, but it can’t be used in any wire. Because in wire line delay, we need to order event sequentially, this is possible only in transport delay mechanism. Therefore, PC wire line delay can be implemented only by using a transport delay mechanism.
5. The condition to implement the simulation delta delay is _______
a) All events must be synchronous
b) The events must have at least one sequential circuit
c) No condition
d) All events must be zero delay event
Explanation:The simulation delta delay model is used to solve the problem of different output for same input between different simulation runs. This occurs when all the events have zero delay and are not properly ordered. So, simulation delta delay model is implemented when the events are with zero delay.
6.What do you mean by a block?
a) An object of architecture
b) Interconnection of two or more signals
c) A part of an entity
d) A sub module in an architecture body
Explanation: The sub modules in architecture can be described as blocks. A block is a unit of module structure, with its own interface, connected to other blocks or ports. For example, while designing CPU, one can divide the architecture into blocks in which one may be describing ALU and another may be describing Control signals and so on.
7. What is the scope of variables or signals declared in the block statement?
a) Global to the design
b) Local to the architecture
c) Local to the block itself
d) Local to the entity of which architecture is defined
Explanation: The variables or signals declared in the BLOCK are available local in the block statement only. However, a block can declare constants, types, components, subprograms apart from variables or signals. But, anything declared in the block can be used in the block only
8. Which of the following defines the interface to the block?
a) Block declaration part
b) Block header
c) Block statement part
d) Generic declaration part
Explanation: A block header defines the interface to an entity. The values of generics or components associated with the block are defined in the block header. It uses a port map and generic map functions to declare and map components and generics with the block.
9. Guarded block has an extra ________ expression.
a) Conditional
b) Declarative
c) Block
d) Guard
Explanation: VHDL has two types of block which are Simple blocks and guarded blocks. Guarded blocks have an extra guard expression. The role of guard expression is to control the execution of guarded block. The guarded statements in a guarded block are executed only when the guard expression is TRUE.
10. What should be the type of the value of guard expression?
a) BOOLEAN
b) INTEGER
c) REAL
d) BIT_VECTOR
Explanation: The type of result of guard expression should be BOOLEAN which may take only two values either TRUE or FALSE. The statements under guarded block are executed only when the result of guard expression is TRUE. Therefore, it is mandatory to have an expression with BOOLEAN output.