1. Which of the following modeling style follows the sequential processing of instructions?
a) Dataflow modeling
b) Behavior modeling
c) Structural modeling
d) Component modeling
Explanation: Behavior modeling uses sequential processing whereas dataflow and structural modeling uses concurrent statements. In sequential statements, the instructions are executed one after another whereas concurrent statements are executed simultaneously.
2. __________ modeling uses logic gates and basic blocks to describe the functionality of system.
a) Behavioral
b) Structural
c) Dataflow
d) Component
Explanation: In dataflow modeling, the system is represented as flow of control and movement of data. It describes how data flows from input to output by using primitive logic functions. Unlike behavioral modeling, it uses concurrent statements and logic functions.
3. Structural style use processes.
a) True
b) False
Explanation: Structural style does not use processes since it just describe the graphical representation of system. It doesn’t need process statements. Process statements are required to describe the behavior and not structure. Therefore, structural doesn’t need processes.
4. Component instantiation is the part of __________ modeling.
a) Behavior
b) Component
c) Dataflow
d) Structural
Explanation: Component declaration and component instantiation is a part of structural modeling. It first declares the component and then instantiation takes place by using portmap function. Structural modeling is based on netlist.
5.Refer to the code given below, which type of modeling is used to describe the system ?
ARCHITECTURE and_1 OF and_gate IS
begin
process(a, b, y)
begin
IF(a = ‘1’ and b = ‘1’) THEN
y <= ‘1’;
ELSE y <=’0’;
end IF;
END process;
END and_1;
a) Structural
b) Component
c) Dataflow
d) Behavioral
Explanation: Above shown code is for AND gate and it is using process statement. The code gives information about output values for different combinations of input values. Therefore, the code given is behavioral style of modeling.
6. Which logic function is described in the code given below ?
ARCHITECTURE my_func OF my_logic IS
begin
process(a, b, y)
begin
IF(a = ‘0’ and b = ‘0’) THEN
y <= ‘0’;
ELSIF (a = ‘1’ and b= ‘1’) THEN
y<= ‘0’;
ELSE y <= ‘1’;
END if;
END process;
END my_func;
a) AND
b) EXOR
c) OR
d) EXNOR
Explanation:The modeling shown is behavioral modeling. The output y is low for 00 and 11 else the output is high. Therefore, the given logic is for exclusive OR gate. Since in EXOR he output is high for 01 and 10 which is shown in the code given.
7. Ports are known as _________ to the component.
a) Structure
b) Behavior
c) Function
d) Interface
Explanation: Ports are used to declare the inputs and outputs of a specific component in the structural modeling. They act as an external interface of the component since it tells the number of input and outputs a component can have
8. What is the use of a function called port map()?
a) Component declaration
b) Defining identifiers
c) Component instantiation
d) Defining inputs and outputs
Explanation: The function portmap() is used for component instantiation. By taking instances of input output ports declared at the time of declaration, the component is instantiated. Basically, to define the relation of component with the signals, we use portmap().
9. The signal assignment is considered as a ________
a) Concurrent statement
b) Sequential statement
c) Subprogram
d) Package declaration statement
Explanation: The signal assignment statement is typically considered a concurrent statement rather than a sequential statement. However, the statement can be used as a sequential statement as well but has a side effect of obeying the general rules for when the left operand is actually updated.
10. How can we use an assignment statement as a sequential assignment?
a) By using keyword WAIT
b) By using a delay mechanism
c) By using conditional statements
d) By using it in any process
Explanation: The assignment statements can appear either in architecture or in a process. According to this only, the signal assignment is classified as a concurrent and sequential assignment. If the signal assignment is done in a process, then it is a sequential assignment, otherwise it is a concurrent assignment