1. Which of the following is not a back end EDA tool?
a) Routing tools
b) Placement tools
c) Simulators
d) Floor planning tools
Explanation: Simulators are the tools which are used at the front end and all other tools are used at the back end.
2. The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________
a) Verification
b) Synthesis
c) Simulation
d) Optimization
Explanation: Synthesis means to generate netlist, i.e. describing the circuit by the relation between inputs and outputs by using logic equations. Simulation is whereas to check the correctness of VHDL code and Optimization is to optimize the netlist; optimization is performed after the synthesis. Verification similarly uses different EDA tool to perform gate level verification.
3. What is the full form of VHDL?
a) Very High speed Description Language
b) Variable Hardware Description Language
c) Verilog Hardware Description Language
d) Very high speed Hardware Description Language
Explanation: Most people confuse Verilog Hardware Description Language with VHDL but, VHDL means VHSIC Hardware Description Language where VHSIC is the acronym for Very High Speed Integrated Circuits.
4. Place and Route EDA tools are used to take the design netlist and implement the design in the device.
a) True
b) False
Explanation: Place and Route tools are used to take the netlist and implement it on the target device by taking various factors into consideration like Timing constraints and some device information.
5. What is the basic use of EDA tools?
a) Industrial automation
b) Electronic circuits simulation and synthesis
c) Fabrication of Electronics hardware
d) Communication of Electronic devices
Explanation: EDA expands to Electronic Design Automation and these tools are used for synthesis, implementation and simulation of Electronic circuits on the software itself.
6. What are the differences between simulation tools and synthesis tool?
a) Simulators and Synthesis tools works exactly same
b) Simulation finds the error in the code and Synthesis tool corrects the code
c) Simulators are used just to check basic functionality of the circuit and Synthesis tools includes timing constraints and other factors along with simulation
d) Simulators are used to check the performance of circuit and Synthesis tools are for the fabrication of circuits
Explanation: Simulators test basic logic and working of the circuit described in the code and Synthesis allows to take timing factor and other factors into consideration while simulation.
7. VHDL is based on which of the following programming languages?
a) ADA programming language
b) Assembly
c) PHP
d) C
Explanation: The syntax and whole structure of VHDL code is based upon ADA programming language whereas Verilog HDL finds its origin from C language.
8. What is the extension of the netlist file; input to the place and route EDA tools?
a) EDIF
b) CPP
c) TXT
d) SDF
Explanation: EDIF and XNF are the netlist files; whereas SDF is the file of timing information.TXT is the extension of a simple text file and CPP is the C++ source file.
9. Which of the following is not an EDA tool?
a) Quartus II
b) Visual C++
c) MaxPlus II
d) Xilinx ISE
Explanation: Quartus II EDA tool is used for Altera CPLD and FPGA devices. Similarly, Xilinx ISE is used for Xilinx CPLD/FPGA devices. MaxPlus is also an advanced EDA tool for Altera CPLDs. Visual C++ is the compiler for C and C++ languages.
10. An Antifuse programming technology is associated with _________
a) SPLDs
b) CPLDs
c) ASICs
d) FPGAs
Explanation: Antifuse technology is used to burn the information, from place and route tools, into appropriate fuses in the FPGAs.