1. What is the correct syntax for mapping a GENERIC parameter in structural modeling?
a) label : component_name GENERIC MAP(parameter_list) PORT MAP(port_list)
b) label : component_name GENERIC MAP(parameter_list)
c) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)
d) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)
Explanation: Generic is a constant parameter which can be used in structural modeling. But, generic is not a component as such. It can be used as a specification to any component. The correct syntax to use a generic is GENERIC MAP followed by a PORT MAP function
2. It is possible to use a GENERIC parameter as a separate component.
a) True
b) False
Explanation: A Generic is just a constant and hence can’t have any input or output ports. It is only used with any component to describe its specification. For example, any component needs an array of input ports, the index value of that array can be defined by using generic parameter and that generic parameter can be used with PORT MAP to map the ports.
3. A component instantiation statement generates a(n) _______ of the component.
a) Class
b) Behavior
c) Structure
d) Object
Explanation: By ending the component declaration, its object is created which can be used further in the code to use the declared component. The component instantiation statement uses this object and inherits the properties of component declared. These properties include all the ports and their number.
4. The structural code for 4-bit adder is given below.
COMPONENT adder IS
GENERIC (n : INTEGER := 3);
PORT(input : IN BIT_VECTOR(n DOWNTO 0);
output : OUT BIT_VECTOR(n DOWNTO 0));
END COMPONENT;
If user want to convert this in an 8 bit adder, which of the following variable should be changed?
a) n
b) input
c) output
d) component
Explanation: The only way to change it is by changing the value of n. If n is changed from 3 to 7, then it will have 8 input bits and 8 output bits. In this way, by using generic, the whole structure can be altered easily. Also, it may be noted if the value of the generic is not specified, then it will take the value used at the time of entity declaration.
5. What is the other name for implicit mapping?
a) Nominal mapping
b) Positional mapping
c) Explicit mapping
d) Inclusive mapping
Explanation: Implicit mapping is another name for positional mapping in which only ports are specified without using any assignments. Similarly, nominal mapping is the other name for explicit mapping which uses proper assignments to instantiate the component. In VHDL, there are only two types of mapping called Positional and nominal, there is no mapping called inclusive mapping.
6. What does modeling type refer to?
a) Type of ports in entity block of VHDL code
b) Type of description statements in architecture block of VHDL code
c) Type of data objects
d) Type of Signals
Explanation: Modeling refers to the descriptive style we are using to describe our digital system. Modeling type is the type of statement used in architecture block to describe a specific system or circuit. It may define a structure or behavior or anything else.
7. Which of the following is not a type of VHDL modeling?
a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) Component modeling
Explanation: VHDL modeling is of three types. These types are behavioral modeling, dataflow modeling and structural modeling. There is no such modeling called component modeling. However, one can declare components in structural modeling.
8. In behavioral modeling, what do descriptive statements describe?
a) How the system performs on given input values
b) How the design is to be implemented
c) Netlist
d) Concurrent execution
Explanation: Behavioral style specifies what a particular system does in a program. It gives the details of output values corresponding to the set of input values. In general, behavioral modeling use processes to describe the functioning of system, but no detail is provided regarding the design of the system.
9. Which of the following statement is used in structural modeling?
a) portmap()
b) process()
c) if-else
d) case
Explanation: In structural modeling, the graphical representation of the system is described. All the modules, instances or components are defined along with their interconnections. It is defined that how the components are connected to each other by using nets or wires. The portmap() function is used to map the specific component in the design.
10. What is the basic unit of behavioral description?
a) Structure
b) Sequence
c) Process
d) Dataflow
Explanation: The primary unit of a behavior description in VHDL is process which describes the behavior of system on various combinations of inputs. All the system is described by using processes and therefore, process is the basic unit.