1. What is the main purpose of using blocks?
a) To improve reusability
b) To improve conditional execution
c) To improve readability
d) To improve speed of execution
Explanation: Blocks are useful to improve the readability and management of VHDL design. In a high level design, say CPU design, blocks are very useful since it can be divided into blocks which can further be managed easily rather than managing whole code. Another use of block statement is to disable some signals by using guard expression. However, the result of simulation will be same of the code using block and the same without blocks.
2. Guarded blocks are synthesizable.
a) True
b) False
Explanation: In general EDA tools, the guarded blocks are not synthesizable and unguarded blocks doesn’t add any additional functionality to the design and therefore, are usually ignored by synthesis tools. So, it is not much useful to use blocks in non-VITAL designs.
3. Which of the following is better for design partitioning?
a) Guarded block
b) Unguarded block
c) Component instantiation
d) Component declaration
Explanation: Since guarded and unguarded blocks are not synthesizable. So, component instantiation is certainly a better mechanism to handle design partitioning which is completely synthesizable. Therefore, it is recommended to use component instantiation rather than block statements
4. A block can be nested within another block.
a) True
b) False
Explanation: Nesting of blocks is possible in VHDL. A block can be defined within another block. The nested block is called the child block and the other block is called parent block. Also, it is possible to define two signals with same name one in parent block and another in child block.
5. Which of the following is true about guarded blocks?
a) Guarded blocks can have only guarded statements
b) Guarded blocks can have both guarded as well as unguarded statements
c) Guarded blocks are executed when guarded expression is false
d) Guarded expression can have BIT type
Explanation: Guarded blocks can have both types of statements which are guarded and unguarded. Guarded assignment statements are those statements in which an assignment operator is followed by the keyword called GUARDED. For example, q <= GUARDED d AFTER 10 ns; here the assignment statement used is guarded statement
6. Which of the following statement is used to describe regular structures?
a) BLOCK
b) GENERATE
c) USE
d) GUARDED BLOCK
Explanation: Generate statement is used to describe regular structures such as array of blocks, component instances or processes. There are two types of generation schemes one is FOR generation and another is IF generation.
7. What is the use of FOR generation?
a) For describing the exceptional signals
b) For describing the repeating structures
c) For describing half adder circuit
d) For any exceptional cases of structure
Explanation: FOR generation is similar to for loop in traditional programming languages. Therefore, it can be used to describe structures which use some repeating pattern or similar patterns. It is not useful to design half adder by using FOR generation statement.
8. Which of the following is the use of IF generation?
a) To handle repeating pattern of design
b) To handle exceptional cases of design
c) To design full adder circuit
d) To connect input instances with output
Explanation: IF is a conditional generation scheme. It can be used to handle some conditional or exceptional cases of the structure. These exceptions may occur at the boundaries. So, IF generation is generally used at boundaries
9. Which of the following is defined in structural modeling?
a) The structure of circuit
b) Behavior of circuit on different inputs
c) Data flow from input to output
d) Functional structure
Explanation: Structural modeling is the modeling of the circuit at the component level. This type of modeling is used to describe the structure of the system with all the components. Along with components, interconnections between them are also defined
10. Which of the following is not a way of partitioning a design?
a) Component
b) Block statement
c) Processes
d) Generics
Explanation: A VHDL design can be partitioned in many ways but generics is not the way to partition the design. Generics are used as constants. A component can divide the design at a structural level. Similarly, Blocks and processes can divide the behavioral model of the design