1. Which of the following is the basic building block of a design?
a) Architecture
b) Entity
c) Process
d) Package
Explanation: Entity is the basic building block; all the information regarding input and output of the circuit to be designed is declared in Entity.
2. A package in VHDL consists of _________
a) Commonly used architectures
b) Commonly used tools
c) Commonly used data types and subroutines
d) Commonly used syntax and variables
Explanation: Package is a collection of all the commonly used data types and subroutines so that programmers can easily use them in their design without defining the same functions again and again.
3. Complete description of the circuit to be designed is given in _________
a) Architecture
b) Entity
c) Library
d) Configurations
Explanation: Architecture completely describes the circuit; while entity describes just the input and output of the design. Architecture may describe the behavior of the circuit or its structure.
4. In VHDL, Bus is a type of ________
a) Signal
b) Constant
c) Variable
d) Driver
Explanation: Bus is a special kind of signal. It may have its drivers turned off.
5. What is the use of the Configuration statement?
a) To configure the components exactly in design
b) To complete the design process by adding libraries
c) To add more than one entities into a single architecture
d) To add some component in any entity architecture pair
Explanation: Configuration statement is used to bind any component instance with entity architecture pair. It is used to describe the behavior, which is used in almost each entity.
6. What is the use of Generics in VHDL?
a) To turn on and off the drivers
b) To describe architecture
c) To pass information to the entity
d) To divide code into small processes
Explanation: Generics are used to pass the information to entity through parameters. In short, Generics are parameters which passes information to entity. For example, entity has variables for rise time and fall time delay; then the values for both delays can be passed by using Generics.
7. Driver can be seen as a _______ of the signal.
a) Part
b) Type
c) Final value
d) Source
Explanation: Driver is a source on the signal. All of the signals are driven by their Drivers. Any signal may have more than one driver too.
8. Predefined data for an VHDL object is called ________
a) Attribute
b) Constant
c) Generic
d) Library
Explanation: Attribute is the predefined datatype associated with any VHDL object. For example, operating temperature of any device will be its attribute.
9. Which of the following describes the structure of VHDL code correctly?
a) Library Declaration; Entity Declaration; Architecture Declaration; Configurations
b) Entity Declaration; Configuration; Library Declaration; Architecture Declaration
c) Configuration; Library Declaration; Entity Declaration; Architecture Declaration
d) Library Declaration; Configuration; Entity Declaration; Architecture Declaration
Explanation: In any VHDL code, first of all, we have to define libraries and packages we want to use. After Library Declaration part, Entities are declared. When Entities are created, then only we can describe its architecture. Last part in any VHDL code is Configuration.
10. Which of the following statement is true?
a) Package is a collection of Libraries
b) Library is a collection of Packages
c) Entity is a collection of Packages
d) Architecture is a collection of Entities
Explanation: A library consists of many packages which in turn is a collection of data types and subroutines. Entity is a collection of signals and variables and architecture describes the behavior or structure of Entity.