1. What does the architecture of an entity define?
a) External interface
b) Internal functionality
c) Ports of the entity
d) Specifications
Explanation: Basically, entity describes the interface to the VHDL model and its architecture describes the internal view of that entity. It describes the functionality and contains the statements which describe the behavior of entity.
2. What does the declarative part of architecture contain?
a) Declaration of another entity
b) Declaration of libraries and packages
c) Declaration of local signals, constants or subprograms
d) Declaration of Architecture type
Explanation: Declarative part is the optional part of architecture definition. In this section, the local signals, constants, variables or subprograms are declared which are needed in the architecture. The scope of variables declared in this region is limited to the architecture only.
3. Which of the following can be the name of an architecture?
a) arch 1
b) 1arch
c) arch_1
d) architecture
Explanation: The name of architecture is its identifier and hence, it will follow the same rule as that of identifiers. It may contain alphanumeric characters and underscore character starting with alphabet always. Also, name can’t be same as any of the reserved word of VHDL.
4. The statements in between the keyword BEGIN and END are called _______
a) Concurrent statements
b) Netlist
c) Declaration statement
d) Entity function
Explanation: The proper word for the statements between BEGIN and END is Concurrent statements since they are executed concurrently. The code in between BEGIN and END describes the functionality or structure of the entity. BEGIN keyword specifies the starting of code.
5. An entity can’t be described by more than one architecture.
a) True
b) False
Explanation: It is false that an entity can’t have two or more architectures. An entity can be described by using more than one architecture. For an instance, one can define its behavior and another can explain its structure. However, the converse of the statement is not true, one architecture can describe only one entity.
6. Which of the following can’t be declared in the declaration part of the architecture?
a) Signals
b) Subprograms
c) Components
d) Libraries
Explanation: In the declaration part of architecture, the local data objects and subprograms are defined which can be used in the architecture only. However, a library contains packages which are generally used in every VHDL model and they are declared globally at the starting of VHDL code.
7. It is not possible to declare an entity after declaring its architecture
a) True
b) False
Explanation: An entity is required first to describe its architecture. First of all, entity create an external interface of the system after which we can describe the internal view of entity. Until there is no entity, architecture declaration is not possible.
8. Which of the following statements execute faster?
a) Concurrent statements
b) Sequential statements
c) Declaration statements
d) Loop statements
Explanation: Concurrent statements execute faster than sequential statements. Sequential statements are those which are executed one after another whereas concurrent statements execute concurrently or simultaneously. Therefore, concurrent are faster.
9. What is the meaning of the base unit?
a) Smallest possible unit of any physical literal
b) SI unit of any physical literal
c) CGS unit for any physical literal
d) Fundamental building block of any design
Explanation: Base unit is the smallest possible unit for any physical literal by using which we can derive all other units of the same literal. For example, in case of TIME, the base unit is nanosecond. We can create any bigger unit by using nanoseconds. For example 1 microsecond = 1000 nanosecond.
10. Which of the following is only predefined physical literal in VHDL?
a) VOLTAGE
b) TIME
c) CURRENT
d) DISTANCE
Explanation: TIME is the only predefined physical data type in VHDL. The base unit of TIME is nanosecond. TIME literal is defined in the standard package of std library.