1. The memory management and protection mechanisms are disabled when the 80286 is operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
Explanation: In real address mode of 80286, all the memory management and protection mechanisms are disabled
2.The memory management and protection mechanisms are enabled with advanced instruction set when 80286 is operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
Explanation: In virtual address mode, 80286 works with all of its memory management and protection capabilities, with the advanced instruction set.
3. The 80286 is an upward object code compatible with 8086 or 8088 when operated in
a) normal mode
b) real address mode
c) virtual address mode
d) real and virtual address mode
Explanation: The 80286 is operated in two modes, namely real address mode and virtual address mode. In both the modes, the 80286 is compatible with 8086/8088.
4. The 80286 is available in the package as
a) 68-pin PLCC (plastic leaded chip carrier)
b) 68-pin LCC (lead less chip carrier)
c) 68-pin PGA (pin grid array)
d) all of the mentioned
Explanation: The 80286 is available in 68-pin PLCC (plastic leaded chip carrier), 68-pin LCC (lead less chip carrier) and 68-pin PGA (pin grid array) packages.
5. The clock frequency applied at the CLK pin is internally divided by
a) 2
b) 4
c) 8
d) 1
Explanation: The clock frequency is divided by two internally, and is used for deriving fundamental timings for basic operations of the circuit.
6. The 8 address lines, A23-A16 of 80286 are zero during
a) memory transfer
b) address transfer
c) memory to processor transfer
d) I/O transfer
Explanation: The address lines, A23-A16 are zero during I/O transfers.
7.The signals S1 (active low), S2 (active low) are
a) output signals
b) indicate initiation of bus cycle
c) define type of bus cycle with M/IO (active low)
d) all of the mentioned
Explanation: The signals S1 (active low), S2 (active low) are active low status output signals, which indicate initiation of a bus cycle, and with M/IO (active low) and COD/INTA (active low), they define the type of the bus cycle.
8. If M/IO (active low) signal is ‘0’ then it indicates
a) I/O cycle
b) Memory cycle
c) I/O cycle or INTA cycle
d) I/O cycle or HALT cycle
Explanation: If M/IO (active low) signal is ‘0’ then it indicates that an I/O cycle or INTA cycle is in the process, and if it is ‘1’, it indicates that a memory or a HALT cycle is in progress
9. The LOCK (active low) is activated automatically by hardware using
a) XCHG signal
b) Interrupt acknowledge
c) Descriptor table access
d) All of the mentioned
Explanation: The lock pin is used to prevent the other masters from gaining the control of the bus, for the current and the following bus cycles. This pin is activated by a “LOCK” instruction prefix, or automatically by hardware during XCHG, interrupt acknowledge or descriptor table access.
10. The pin that is used to insert wait states in a bus cycle is
a) WAIT
b) BHE (active low)
c) READY (active low)
d) WAIT(active low)
Explanation: The active low READY pin is used to insert wait states in a bus cycle, for interfacing low speed peripherals. This signal is neglected during HLDA cycle.