1. The memory of a microprocessor serves as
a) storage of individual instructions
b) temporary storage for the data
c) storing common instructions or data for all processors
d) all of the mentioned
Explanation: The memory serves the microprocessor in the same way, whether it is a single microprocessor or a multi microprocessor.
2.In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is
a) one processor
b) two processors
c) more than two processors
d) none of the mentioned
Explanation: In a shared bus architecture, only one processor performs bus cycle to fetch instructions or data from the memory.
3. In multiport memory configuration, the processor(s) that address the multiport memory is(are)
a) 1
b) 2
c) 3
d) many
Explanation: The processors P1 and P2 address a multiport memory, which can be accessed at a time by both the processors.
4. The memory space of a processor that is mapped to other processor/processors and vice-versa is known as
a) multi microprocessor system
b) memory technique
c) bus window technique
d) mapping technique
Explanation: The bus window technique is the correct method of interconnection between the processors.
5. The disadvantage of the bus window technique is
a) both processors must know about bus window
b) both processors must know the address map
c) loss of effective local memory space
d) all of the mentioned
Explanation: The disadvantage of bus window technique is that both processors must know implicitly about the existence of a bus window, its size and the address map. It also results in loss of effective local memory space.
6. Bus switches are present in
a) bus window technique
b) crossbar switching
c) linked input/output
d) shared bus
Explanation: In crossbar switching type of interconnection topology, several parallel data paths are possible. Each node of the crossbar represents a bus switch
7. Which of the following is not a type of configuration that is based on physical interconnections between the processors?
a) star configuration
b) loop configuration
c) regular topologies
d) incomplete interconnection
Explanation: Based on the physical interconnections between the processors, the configurations are
i) star configuration
ii) loop or ring configuration
iii) complete interconnection
iv) regular topologies
v) irregular topologies.
8. The configuration, in which all the processing elements are connected to a central switching element, that may be independent processor via dedicated paths is
a) star
b) loop
c) complete
d) irregular
Explanation: The switching element controls the interconnections between the processing elements.
9. The configuration that is not suitable for a large number of processors is
a) star
b) loop
c) complete
d) regular
Explanation: For a large number of processors, the complete interconnection is impractical due to a large number of interconnection paths.
10. The array processor architecture is an example of
a) star
b) loop
c) complete
d) regular
Explanation: In array processor architecture, the processing elements are arranged in a regular fashion