Microprocessor Questions and Answers Part-26

1. The pin that is used for data transfer control and operation termination signals is
a) SINTR
b) EXT
c) DRQ and EXT
d) RQ (active low) or GT (active low)

Answer: c
Explanation: The DRQ and EXT are used for data transfer control and operation termination signals during DMA operations

2.The pin that is used to inform the CPU that the previous operation is completed is
a) RQ (active low)
b) GT (active low)
c) DRQ
d) SINTR

Answer: d
Explanation: The SINTR pins are used by the channels either to inform the CPU that the previous operation is over or to ask for its attention or interference if required, before the completion of the task.

3. The current channel status of program status word contains
a) source and destination address widths
b) bus load limit
c) interrupt control and servicing
d) all of the mentioned

Answer: d
Explanation: The program status word contains the current channel status, which contains source and destination address widths, channel activity, interrupt control and servicing, bus load limit and priority information.

4. Which of the following is an incorporated function to resolve interprocessor communication problems?
a) bus allotment and control
b) bus arbitration
c) priority resolving
d) all of the mentioned

Answer:d
Explanation: To resolve the various bus contention and interprocessor communication problems, different hardware strategies and algorithms are worked out. These incorporated functions like bus allotment and control, bus arbitration and priority resolving into them.

5. The device that deals with the bus access control functions and bus handshake activities is
a) bus allotment controller
b) bus arbiter
c) priority resolver
d) none of the mentioned

Answer: b
Explanation: The bus arbiter or 8289 takes care of bus access control functions and bus handshake activities

6. The clock generator delays the READY signal until the signal _________ goes low
a) DEN (active high)
b) DEN (active low)
c) AEN (active low)
d) AEN (active high)

Answer: c
Explanation: If AEN (active low) is high, the clock generator delays the READY signal till the AEN (active low) goes low.

7.The bus controller relinquishes the bus if
a) READY (active low)
b) LOCK (active high)
c) CBRQ (active low)
d) BPRO (active high)

Answer: b
Explanation: The bus controller does not relinquish (release its control on) the bus, till the LOCK (active low) input is low

8. The signals that are used by the bus arbitration in the independent request method is
a) BREQ (active low)
b) BPRN (active low)
c) CBRQ (active low)
d) All of the mentioned

Answer: d
Explanation: The four active low signals, bus request (BREQ), bus priority in (BPRN), common bus request (CBRQ) and bus priority out (BPRO) are used for bus arbitration.

9. The signal that is used to drive a priority resolving network that actually accepts the bus request inputs is
a) BREQ (active low)
b) BPRN (active low)
c) CBRQ (active low)
d) BPRO (active low)

Answer: a
Explanation: The BREQ (active low) is used to drive a priority resolving network that actually accepts the bus request inputs from all the masters and derives the priority outputs which further drive the BPRN (active low) inputs of all the masters.

10. Which of the following is the simplest and cheapest method of bus arbitration?
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned

Answer: a
Explanation: The daisy chaining method is the simplest one, as it has less hardware complexity.