1. In direct memory access mode, the data transfer takes place
a) directly
b) indirectly
c) directly and indirectly
d) none of the mentioned
Explanation: In direct memory access mode, the data may transfer directly without the interference from the CPU.
2. In 8257 (DMA), each of the four channels has
a) a pair of two 8-bit registers
b) a pair of two 16-bit registers
c) one 16-bit register
d) one 8-bit register
Explanation: The DMA supports four channels, and each of the channels has a pair of two 16-bit registers, namely DMA address register and a terminal count register.
3.The common register(s) for all the four channels of 8257 is
a) DMA address register
b) Terminal count register
c) Mode set register and status register
d) None of the mentioned
Explanation: The two common registers for all the four channels of DMA are mode set register and status register.
4. In 8257 register format, the selected channel is disabled after the terminal count condition is reached when
a) Auto load is set
b) Auto load is reset
c) TC STOP bit is reset
d) TC STOP bit is set
Explanation: If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is reached, and it further prevents any DMA cycle on the channel
5. The IOR (active low) input line acts as output in
a) slave mode
b) master mode
c) master and slave mode
d) none of the mentioned
Explanation: The IOR (active low) is an active low bidirectional tristate input line, that acts as input in the slave mode, and acts as output in the master mode. In master mode, this signal is used to read data from a peripheral during a memory write cycle.
6. The IOW (active low) in its slave mode loads the contents of a data bus to
a) 8-bit mode register
b) upper/lower byte of 16-bit DMA address register
c) terminal count register
d) all of the mentioned
Explanation: In its slave mode, the IOW (active low) loads the contents of a data bus to 8-bit mode register, upper/lower byte of 16-bit DMA address register or terminal count register.
7. The pin that disables all the DMA channels by clearing the mode registers is
a) MARK
b) CLEAR
c) RESET
d) READY
Explanation: The RESET pin which is asynchronous input disables all the DMA channels by clearing the mode registers, and tristate all the control lines
8.The pin that requests the access of the system bus is
a) HLDA
b) HRQ
c) ADSTB
d) None of the mentioned
Explanation: The hold request output requests the access of the system bus.
9.The pin that is used to write data to the addressed memory location, during DMA write operation is
a) MEMR (active low)
b) AEN
c) MEMW (active low)
d) IOW (active low)
Explanation: The MEMW (active low) is used to write data to the addressed memory location, during DMA write operation.
10. The pin that strobes the higher byte of the memory address, generated by the DMA controller into the latches is
a) AEN
b) ADSTB
c) TC
d) None of the mentioned
Explanation: The pin ADSTB strobes the higher byte of the memory address, generated by the DMA controller into the latches.