Embedded System Questions and Answers Part-25

1. Which of the following support virtual memory?
a) segmentation
b) descriptor
c) selector
d) paging

Answer: d
Explanation: The paging mechanism supports the virtual memory. Paging helps in creating virtual address space which has a major role in memory management.

2. What does DPL in the descriptor describes?
a) descriptor page level
b) descriptor privilege level
c) direct page level
d) direct page latch

Answer: b
Explanation: The descriptor privilege level is used to restrict access to the segment which helps in protection mechanism. It acquires two bit of the descriptor.

3. What does “S” bit describe in a descriptor?
a) descriptor type
b) small type
c) page type
d) segmented type

Answer: a
Explanation: The S bit determines whether it is a system segment or a normal segment. When the S bit is set, it might be a code segment or a data segment. If the S bit clears, it is a system segment.

4. How many regions are created by the memory range in the ARM architecture?
a) 4
b) 8
c) 16
d) 32

Answer: b
Explanation: The memory protection unit in the ARM architecture divides the memory into eight separate regions. Each region can be small as well as big ranging from 4 Kbytes to 4 Gbytes.

5. How many bits does the memory region in the ARM memory protection unit have?
a) 1
b) 2
c) 3
d) 4

Answer: c
Explanation: The memory region possesses three bits which are the cacheable bit, bufferable bit and access permission bit

6. Which of the following uses a priority level for permitting data?
a) ARM memory management unit
b) ARM protection memory management unit
c) Bus interface unit
d) Execution unit

Answer: b
Explanation: In the ARM protection architecture, the memory is divided into some regions of size 4 Kbytes to 4 Gbytes. These regions possess bits called the cacheable bit, buffer bit, and access permitted bits. The regions are numbered as per priority level for which the permission bits takes the precedence if any of the regions gets overlapped.

7. What type of bit in the ARM memory mimics to that of the protection unit of ARM management unit?
a) permission bit
b) buffer bit
c) cacheable bit
d) access permission bit

Answer: a
Explanation: The ARM architecture memory protection unit divides the memory range into different regions of size ranging from 4 Kbytes to 4 Gbytes. Each region is associated with certain bits called the cacheable bit, buffer bit, and access permitted bit. These bits are similar to the permission bit in the ARM memory management unit architecture which is stored in the control register.

8. Which of the following bits are used to control the cache behaviour?
a) cacheable bit
b) buffer bit
c) cacheable bit and buffer bit
d) cacheable bit, buffer bit and permission access bit

Answer: c
Explanation: The cacheable bit and the buffer bit are used to control the behaviour of cache. Depending on the cacheable bit and the buffer bit, the memory access will complete successfully

9. Which of the following unit provides security to the processor?
a) bus interface unit
b) execution unit
c) peripheral unit
d) memory protection unit

Answer: d
Explanation: The memory management unit and the memory protection unit provides security to the processor by trapping the invalid memory accesses before they corrupt other data.

10. Which of the following includes a tripped down memory management unit?
a) memory protection unit
b) memory real mode
c) memory management unit
d) bus interface unit

Answer: a
Explanation: The memory protection unit allows a tripped memory down memory management unit in which the memories are partitioned and protected without any address translation. This can remove the time consumption in the address translation thereby increases the speed