1. What is the worst case delay of the burst refresh in 4M by 1 DRAM?
a) 0.4ms
b) 0.2ms
c) 170ns
d) 180ns
Explanation: A 4M by 1 DRAM have 1024 refresh cycles. Bursting delay will be 0.2ms that are, the worst case delay is 1024 times larger than that of the single refresh cycle. The distributed delay is about 170ns..
2. Which refresh techniques depends on the size of time critical code for calculating the refresh cycle?
a) burst refresh
b) distributed refresh
c) refresh cycle
d) software refresh
Explanation: Most of the system uses the distributed method and depending on the size of the time critical code, the number of refresh cycles can be calculated.
3. Which of the following uses a timer for refresh technique?
a) RAS
b) CBR
c) software refresh
d) CAS
Explanation: The software refresh performs the action by using a routine to periodically cycle through the memory and refreshes. It uses a timer in the program generating an interrupt. This interrupt performs the refreshing part in the DRAM.
4. What is the main disadvantage in the software refresh of the DRAM?
a) timer
b) delay
c) programming delay
d) debugging
Explanation: Debugging in software refresh is very difficult to perform because they may stop the refreshing and if the refreshing is stopped, the contents get lost.
5. Which refresh technique is useful for low power consumption?
a) Software refresh
b) CBR
c) RAS
d) Burst refresh
Explanation: CBR that is, CAS before RAS refresh is the one which is commonly used. It has low power consumption quality because it does not have address bus and the buffers can be switched off. It is worked by using an internal address counter which is stored on the memory chip itself and this can be incremented periodically.
6. Which refreshing techniques generate a recycled address?
a) RAS
b) CBR
c) Distributed refresh
d) Software refresh
Explanation: The row address is placed on the address bus and the column address is held off which generates the recycle address. The address generation is done by an external hardware controller.
7. Which of the following uses a software refresh in the DRAM?
a) 8086
b) 80386
c) Pentium
d) Apple II personal computer
Explanation: The Apple II personal computer has a particular memory configuration, periodically the DRAM gets blocked and is used for video memory accessing to update the screen which can refresh the DRAM.
8. How do CBR works?
a) by asserting CAS before RAS
b) by asserting CAS after RAS
c) by asserting RAS before CAS
d) by asserting CAS only
Explanation: CBR works by an internal address counter which is periodically incremented. The mechanism is based on CAS before RAS. Each time when RAS is asserted, the refresh cycle performs and the counter is incremented.
9. Which of the refresh circuit is similar to CBR?
a) software refresh
b) hidden refresh
c) burst refresh
d) distribute refresh
Explanation: In the hidden refresh, the refresh cycle is added to the end of a normal read cycle. The RAS signal goes high and is then asserted low. At the end of the read cycle, the CAS is still asserted. This is similar to the CBR mechanism, that is, toggling of the RAS signal at the end of the read cycle starts a CBR refresh cycle.
10. Which technology is standardized in DRAM for determining the maximum time interval between the refresh cycle?
a) IEEE
b) RAPID
c) JEDEC
d) UNESCO
Explanation: The maximum time interval between refresh cycle is standardized by JEDEC, Joint Electron Device Engineering Council which is an independent semiconductor engineering trade organization. This standardized JEDEC in DRAM is specified in the manufacturer’s chip specification