1. ISP stands for _________
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
Explanation: Instruction Set Processor
2. The internal components of the processor are connected by _______
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
Explanation: The processor BUS is used to connect the various parts in order to provide a direct connection to the CPU.
3. ______ is used to choose between incrementing the PC or performing ALU operations.
a) Conditional codes
b) Multiplexer
c) Control unit
d) None of the mentioned
Explanation: The multiplexer circuit is used to choose between the two as it can give different results based on the input.
4. The registers, ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
c) information path
d) data path
Explanation: The Operational and processing part of the CPU are collectively called as a data path.
5. _______ is used to store data in registers.
a) D flip flop
b) JK flip flop
c) RS flip flop
d) None of the mentioned
Explanation: D flip flop
6. During the execution of the instructions, a copy of the instructions is placed in the ______
a) Register
b) RAM
c) System heap
d) Cache
Explanation: Cache
7. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?
a) A
b) B
c) Both take the same time
d) Insufficient information
Explanation: The performance of a system can be found out using the Basic performance formula.
8. A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of the mentioned
Explanation: Pipe-lining is the process of improving the performance of the system by processing different instructions at the same time, with only one instruction performing one specific operation.
9. For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?
a) ISA
b) ANSA
c) Super-scalar
d) All of the mentioned
Explanation: In super-scalar architecture, the instructions are set in groups and they’re decoded and executed together reducing the amount of time required to process them.
10. The clock rate of the processor can be improved by _________
a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using the overclocking method
d) All of the mentioned
Explanation: The clock rate(frequency of the processor) is the hardware dependent quantity it is fixed for a given processor.