1. When the R/W bit of the status register of the DMA controller is set to 1.
a) Read operation is performed
b) Write operation is performed
c) Read & Write operation is performed
d) None of the mentioned
Explanation: Read operation is performed
2. The controller is connected to the ____
a) Processor BUS
b) System BUS
c) External BUS
d) None of the mentioned
Explanation: The controller is directly connected to the system BUS to provide faster transfer of data.
3. Can a single DMA controller perform operations on two different disks simultaneously?
a) true
b) false
Explanation: The DMA controller can perform operations on two different disks if the appropriate details are known.
4. The technique whereby the DMA controller steals the access cycles of the processor to operate is called __________
a) Fast conning
b) Memory Con
c) Cycle stealing
d) Memory stealing
Explanation: The controller takes over the processor’s access cycles and performs memory operations.
5. The technique where the controller is given complete access to main memory is __________
a) Cycle stealing
b) Memory stealing
c) Memory Con
d) Burst mode
Explanation: The controller is given full control of the memory access cycles and can transfer blocks at a faster rate.
6. The controller uses _____ to help with the transfers when handling network interfaces.
a) Input Buffer storage
b) Signal enhancers
c) Bridge circuits
d) All of the mentioned
Explanation: The controller stores the data to transfer in the buffer and then transfers it.
7. To overcome the conflict over the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
d) None of the mentioned
Explanation: The BUS arbitrator is used to overcome the contention over the BUS possession.
8. The registers of the controller are ______
a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits
Explanation: 32 bits
9. When the process requests for a DMA transfer?
a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) process is temporarily suspended & Another process gets executed
Explanation: The process requesting the transfer is paused and the operation is performed, meanwhile another process is run on the processor.
10. The DMA transfer is initiated by _____
a) Processor
b) The process being executed
c) I/O devices
d) OS
Explanation: The transfer can only be initiated by an instruction of a program being executed.