1. We have no use of having silicon customization?
a) True
b) False
Explanation: It achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extension, optimization for size, debug support, etc.
2. Which of the following has the same instruction set as ARM7?
a) ARM6
b) ARMv3
c) ARM71a0
d) ARMv4T
Explanation: The original ARM7 was based on the earlier ARM6 design and used the same ARM3 instruction set.
3. What are t, d, m, I stands for in ARM7TDMI?
a) Timer, Debug, Multiplex, ICE
b) Thumb, Debug, Multiplier, ICE
c) Timer, Debug, Modulation, IS
d) Thumb, Debug, Multiplier, ICE
Explanation: The ARM7TDMI(ARM7 + 16 bit Thumb + JTAG Debug + fast Multiplier + enhanced ICE) processor implements the ARM4 instruction set.
4. ARM stands for _________
a) Advanced RISC Machine
b) Advanced RISC Methadology
c) Advanced Reduced Machine
d) Advanced Reduced Methadology
Explanation: ARM, originally Acorn RISC Machine, later Advanced RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computing processors.
5. What are the profiles for ARM architecture?
a) A,R
b) A,M
c) A,R,M
d) R,M
Explanation: ARMv7 defines 3 architecture “profiles”:
A-profile, Application profile
R-profile, Real-time profile
M-profile, Microcontroller profile.
6. ARM7DI operates in which mode?
a) Big Endian
b) Little Endian
c) Both big and little Endian
d) Neither big nor little Endian
Explanation: Big Endian configuration, when BIGEND signal is HIGH the processor treats bytes in memory as being in Big Endian format. When it is LOW memory is treated as little Endian.
7. In which of the following ARM processors virtual memory is present?
a) ARM7DI
b) ARM7TDMI-S
c) ARM7TDMI
d) ARM7EJ-S
Explanation: ARM7DI is capable of running a virtual memory system. The abort input to the processor may be used by the memory manager to inform ARM7DI of page faults.
8. How many instructions pipelining is used in ARM7EJ-S?
a) 3-Stage
b) 4-Stage
c) 5-Stage
d)2-stage
Explanation: A five-stage pipelining is used, consisting of Fetch, Decode, Execute, Memory, and Writeback stages. A six-stage pipelining is used in Jazelle state, consisting of Fetch, Jazelle, Execute, Memory, and Writeback stages.
9. How many bit data bus is used in ARM7EJ-s?
a) 32-bit
b) 16-bit
c) 8-bit
d) Both 16 and 32 bit
Explanation: The ARM7EJ-s processor has a Von Neumann architecture. This feature is a single 32-bit data bus that carries both instructions and data. Only load, store, and swap instructions can access data from memory. Data can be 8- bit.
10. What is the cache memory for ARM710T?
a) 12Kb
b) 16Kb
c) 32Kb
d) 8Kb
Explanation: The ARM710T is a general purpose 32-bit microprocessor with 8Kb cache, enlarged write buffer and memory management unit combined in a single chip.