1. MSP430 uses vectored interrupts?
a) true
b) false
c) cant be said
d) depends on the conditions
Explanation: MSP430 has vectored interrupts i.e. the address of each ISR is stored in a vector table, that’s why it has vectored interrupts.
2. Which of the following is true?
a) interrupts are required to wake a CPU from sleep
b) same vector address associated with multiple flags
c) most interrupts are maskable
d) all of the mentioned
Explanation: All of the above mentioned statements are true i.e. interrupts are required to wake a CPU from sleep, same vector address associated with multiple flags and most of the interrupts are maskable.
3. After the interrupt has occurred, the stack is filled with ______________
a) return address
b) status register
c) return address & status register
d) none of the mentioned
Explanation: When an interrupt had occurred, the top place of the stack is filled with the return address, so that immediately after the reti instruction the pointer moves to the main program, the stack is also filled with the bits of the status register so that all the temporary values get stored in it.
4. What is the purpose of __interrupt() function?
a) it is used to enable the interrupt
b) it is used to disable the interrupt
c) it denotes that the routine is an ISR
d) all of the mentioned
Explanation: The purpose of __interrupt() function is to denote that the routine is an ISR.
5. What is the purpose of .intvec assembler directive?
a) it creates an interrupt vector entry that points to an interrupt routine name
b) one is used for storage, other for display
c) one stores locally other stores globally
d) the two are the same
Explanation: The .intvec directive creates an interrupt vector entry that points to an interrupt routine name.
6. For enabling any interrupt, firstly _____________
a) GIE=0
b) GIE=1
c) None of the mentioned
d) GIE=0 & 1
Explanation: If GIE is set to 1, then only other hardware interrupts are enabled.
7. Nonmaskable vectors are stored at different vector locations?
a) true
b) false
c) cant be said
d) depends on the conditions
Explanation: Nonmaskable interrupts are stored in the same vector location, it may be of higher or the lower priority.
8. Which of the following can generate a nonmaskable interrupt?
a) access violation to flash memory, ACCVIFG
b) timer_A interrupt
c) compare / capture interrupt
d) all of the mentioned
Explanation: A nonmaskable interrupt is generated by an access violation to flash memory, ACCVIFG.
9. External RST/NMI pin is a nonmaskable interrupt?
a) true
b) false
c) cant be said
d) depends on the conditions
Explanation: Yes, external RST/NMI pin is a nonmaskable interrupt( The function of the RST/NMI pin is configured in the control register for the watchdog timer module, WDTCTL).
10.How many cycles are used by MSP430, when reti instruction is executed?
a) 3
b) 4
c) 5
d) depends on the conditions
Explanation: When reti instruction is executed, five cycles are used because it firstly pops the stack register completely and then takes the top of the stack into the PC to return to the next address of the main program.