a) Status and Control unit b) DDR c) Register select d) None of the mentioned
View QuestionDDR stands for _________
a) Data Direction Register b) Data Decoding Register c) Data Decoding Rate d) None of the ...
View QuestionIn the output interface of the parallel port, along with the valid signal ______ is also sent.
a) Data b) Idle signal c) Interrupt d) Acknowledge signal Answer: b Explanation: The idle ...
View QuestionThe Status flag circuit is implemented using _____
a) RS flip flop b) D flip flop c) JK flip flop d) Xor circuit Answer: ...
View QuestionIn a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.
a) Valid bit b) Idle bit c) Interrupt enable bit
View QuestionThe disadvantage of using a parallel mode of communication is ______
a) It is costly b) Leads to erroneous data transfer c) Security of data d) All ...
View QuestionThe output of the encoder circuit is/are ______
a) ASCII code b) ASCII code and the valid signal c) Encoded signal d) None of ...
View QuestionThe best mode of connection between devices which need to send or receive large amounts of data over a short distance is _____
a) BUS b) Serial port c) Parallel port d) Isochronous port Answer: c Explanation: The parallel port ...
View QuestionTo overcome multiple signals being generated upon a single press of the button, we make use of ______
a) Generator circuit b) Debouncing circuit c) Multiplexer d) XOR circuit Answer: b
View QuestionThe _____ circuit enables the generation of the ASCII code when the key is pressed.
a) Generator b) Debouncing c) Encoder d) Logger Answer: c Explanation: ...
View Question