a) Acknowledge signal
b) Interrupt signal
c) WMFC signal
d) None of the mentioned
Answer: b
Explanation: The controller raises an interrupt signal to notify the processor that the transfer was complete.
Related Posts
_____________ signal is used as an acknowledgement signal by the slave in Multiple cycle transfers.
Which is fed into the BUS first by the initiator?
The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
The time for which the data is to be on the BUS is affected by __________
The delays caused in the switching of the timing signals is due to __________
In synchronous BUS, the devices get the timing signals from __________
The device which interacts with the initiator is __________
Join The Discussion