a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
Answer: c
Explanation: This is a method of accessing the I/O devices which gives the complete power to the devices, enabling them to intimate the processor when they’re ready for transfer.
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The time for which the data is to be on the BUS is affected by __________
The delays caused in the switching of the timing signals is due to __________
In synchronous BUS, the devices get the timing signals from __________
The device which interacts with the initiator is __________
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